Performance Analysis of Timing-Speculative Processors

We propose a framework to estimate the number of timing errors experienced by an application as it runs on timing-speculative processor. It takes hybrid approach combining accurate gate-level dynamic analysis engine find in processor’s control network with fast architecture-level execution-driven simulator based path activation model datapath. develop instruction-level error that estimates likelihood instruction experiencing error, capturing effects process and data variations well inter-instruction correlations caused recovery scheme used Finally, we utilize two well-known laws applied statistics, law small numbers large numbers, estimate, bounded inaccuracy, total specific application. Our experiments show combination running its input can change performance much 25 percent, demonstrating application-specific is necessary for evaluation processors should be inform design decisions assess suitability applications speculation.